000			nam a22 7a 4500
999			_c25 _d25
003			DUET_LibPGT_2014_08_22
005			20170817221340.0
008			170817b xxu||||| |||| 00| 0 eng d
027			_qDICE 14012
040			_cKAIST
082			_aDICE 14012
100			_4Mohammad Abdur Rouf
245			_aControl Flow Vulnerability: Modeling, Evaluation and Low-cost Hardware/Software Solutions. _cMohammad Abdur Rouf
260			_aKorea Adanced Institute of Technology (KAIST) _bKAIST Library _c23-05-2014
300			_axi, 111p. : hard binding ; 30 cm
500			_aEmbedded systems are becoming more susceptible to transient errors because of miniaturization of VLSI circuits and reduction of voltage levels. These errors affect the processor’s pipeline and hence its data and control flows. Data errors are two types: (i) computational errors due to incorrect results from functional units, and (ii) memory errors occur due to corruption of the stored data. However, errors in control flow can change the program’s execution sequence, which might be catastrophic for safety-critical applications. Vulnerabilities to transient errors in a microprocessor system were previously performed for instruction queues, execution units, register files, read/write buffers, instruction and data caches, and translation look aside buffers. However, control flow vulnerabilities have not been explored extensively. The author makes a model to evaluate the program’s Vulnerability Factor of Control Flow (VFCF) in a pipelined processor. VFCF is investigated for a program under different compiler optimization strategies. It is observed that different programs show various degrees of VFCF against compiler optimizations flags. To better evaluate the VFCF, author redevelops VFCF model referred to as CFV model which integrates normalized instructions, branches, taken branches and execution cycles. Conventional techniques are either software-based or hardware-based to overcome control flow vulnerabilities. Software-based techniques suffer from increased code-size overhead and have a negative impact on energy consumption and performance degradation. On the other hand, hardware-based schemes incur high hardware and area costs. Author proposes two low-cost control flow vulnerability reduction mechanisms: (i) hardware-based low-cost control flow error checking scheme and (ii) code transformation scheme. Low-cost Control Flow Error Checking (CFEC) scheme is a hardware-based technique that exploits available redundancies in the microprocessor’s pipeline. A branch target buffer (BTB) stores the target addresses of taken branches, a short backward branch (SBB) detector stores short backward branch targets and an arithmetic logic unit (ALU) generates branch target addresses using the low-order branch displacement bits of branch instructions. The proposed CFEC scheme utilizes these redundancies to detect and recover from control-flow errors in the pipeline with negligible energy overhead of 0.9% and performance overhead of 0.8%, while error coverage ranges from 86% to 99%. Secondly, the author applies code transformations such as code replication, condition merging, and selected combination of these transformations to application programs. The transformed code with the use of compiler optimization flags reduce CFV significantly. The effects of code transformations on CFV are verified for two embedded architectures: ARM and MIPS. The CFV is reduced by 18% to 98% and on the average by 62% for ARM programs. In the MIPS programs, CFV is reduced by 55% on the average. The combined reliability and performance metric CFV × CPI is also reduced by 63% for ARM and by 65% for MIPS.
505			_uhttps://drive.google.com/open?id=0B20VKNntsoafT2pNYWc5dW5sbDA
630			_lEnglish
650			_2Control-flow error _vRealiability _xLow-power _yComputer Architecture
856			_3Fulltext Available _uhttps://drive.google.com/open?id=0B20VKNntsoafT2pNYWc5dW5sbDA
942			_2ddc _cPGT